1. Field of the Invention
The present invention relates to semiconductor memory devices and method for testing a semiconductor therewith, and more particularly to a semiconductor memory device having a test mode and a method for testing a semiconductor therewith.
2. Description of the Background Art
In recent years, integration of a DRAM has been quadrupled every new generation. The higher integration in DRAM means longer test time. Hence, various techniques for reducing test cost by shortening the test time has been proposed.
One technique for reducing the test cost is a so-called burn-in test. In the burn-in test, a number of DRAMs are placed on a single test board and driven under the conditions of high temperature and high power supply voltage to accelerate the occurrence of initial failure. With this technique, the test cost of one DRAM can be reduced because a number of DRAMs are tested together.
Conventionally, however, as a new test board has to be manufactured along with the progress in DRAM generation, the test cost tends to increase. In addition, lately other tests are also required to be performed during the burn-in test, and a test-facilitating design (such as test mode) has been proposed to meet the need.
Further, in order to reduce chip area, shrinkage of layout area of test-related circuitry is needed as well as of other peripheral circuitry.